雙鎖相環擴頻和冗余時鐘發生器ad9577數據表

　　The AD9577 provides a multioutput clock generator function， along with two on-chip phase-locked loop cores， PLL1 and PLL2， optimized for network clocking applications. The PLL designs are based on the Analog Devices， Inc.， proven portfolio of high performance， low jitter frequency synthesizers to maximize network performance. The PLLs have I2 C programmable output frequencies and formats. The fractional-N PLL can support spread spectrum clocking for reduced EMI radiated peak power. Both PLLs can support frequency margining. Other applications with demanding phase noise and jitter requirements can benefit from this part. The first integer-N PLL section （PLL1） consists of a low noise phase frequency detector （PFD）， a precision charge pump （CP）， a low phase noise voltage controlled oscillator （VCO）， a programmablefeedback divider， and two independently programmable output dividers. By connecting an external crystal or applying a reference clock to the REFCLK pin， frequencies of up to 637.5 MHz can be synchronized to the input reference. Each output divider and feedback divider ratio is I2 C programmed for the required output rates.