DshanMCU-R128s2芯片參數

芯片特性

- XuanTie 64 bit RISC V C 906 CPU , up to 480 MHz
- HiFi5 Audio DSP up to 400 MHz
- Arm M33 Star MCU , up to 192 MHz

- Memories

  - 1MB SRAM

  - SiP 8 MB/16 MB Flash

  - 8 MB H S PSRAM in R128 S 1
  - 8 MB LS PSRAM & 8 MB HS PSRAM in R128 S2
  - 32 MB HS PSRAM in R128 S3
  - 2048 bit efuse

- Image and Graphics

  - Supports Graphic 2D accelerator with rotate, mixer, and 4 layers
  - Supports RGB output interface, up to 1024 x 768 @60 fps
  - Supports display engine

- Video Input

  - 8 bit parallel CSI interface
  - Supports both online and offline mode for JPEG encoder
  - Supports JPEG encoder, 1920 x 108 8

- Analog Audio Codec

  - 2 DAC channels 24 bit audio codec for R128 S1 and R128 S2
  - 1 DAC channel 24 bit for R128 S3
  - 3 ADC channels
  - Supports USB audio playback
  - Up to 119 dB SNR during DAC playback path (signal through DAC and lineout with A weighted filter)
  - Up to 98 dB SNR during ADC record path (signal through PGA and ADC with A weighted filter)

- One I2S/TDM/PCM external inte rface (I2S0

- Security Engine

  - Symmetrical algorithm: AES, DES, 3DES
  - Hash algorithm: MD5, SHA1, SHA224, SHA256, SHA384, SHA512, HMAC
  - Asymmetrical algorithm: RSA512/1024/2048bit
  - S upports TRNG

- External Peripherals

  - One USB 2.0 DRD
  - Up to 3 UART controllers (UART 0, UART1, UART2)
  - Up to 2 SPI controllers (SPI0, SPI1)
  - Up to 2 TWIs
  - One CIR RX and one CIR TX
  - Up to 8 PWM channels (PWM[ 7 0
  - Up to 7 GPADC input channels (R128 S1 & R128 S2)/8 channels (R128 S3)
  - One LEDC used to control the external intelligent control LED lamp

- Package

  - QFN80, 0.35 mm pitch, 8 mm x 8 mm body

GPIO 復用

For R128-S1/S2

For R128-S3

信號描述

R128-S1/R128-S2 與 R128-S3 的引腳區別